??? 08/24/11 02:03 Read: times |
#183447 - Best is normally in the middle Responding to: ???'s previous message |
Yes, from a technological standpoint, a full crossbar is a bad design. It gives the developers the most choices, but at a too high design cost.
But the current design is going flat out in the other direction. Much too stupid - i.e. wasting the transistors doing the wrong thing. We all know that requirements changes do come in. Right now, you may have to rip and reroute quite a huge number of pins just because you needed one single configuration change. And first trying out a design change by patching an existing unit can be really ugly. The trick here is that there are alternative crossbar solutions where the same number of transistors can get 90-95% of the way towards a full crossbar if we don't require "any-to-any" but just want to solve the equation of "smallest possible change", i.e. a minimum of processor pins to reallocate after an reconfiguration. If each signal have 2-4 alternatives, then you need a minimum of transistors/signal compared to a full matrix. But you still get very much bang for the buck as long as peripherial A never shares more than one pin with any other peripherial. You can get even further if each peripherial signal is allowed to route to 2-4 cross-routes, and every pin is allowed to map to 2-4 cross-routes (of course with different permuations on the two sides). Still few transistors but a very high number of configuration alternatives. In the real world, there is seldom any optimums - either they are impossible to find or have a too high cost. But good approximations can often be found. |
Topic | Author | Date |
C8051F120 SPI0 and UART1 | 01/01/70 00:00 | |
priority crossbar | 01/01/70 00:00 | |
Caution on Using SiLabs Parts | 01/01/70 00:00 | |
Hurtful choice | 01/01/70 00:00 | |
the story | 01/01/70 00:00 | |
Best is normally in the middle | 01/01/70 00:00 | |
TY | 01/01/70 00:00 | |
I meant port pins | 01/01/70 00:00 | |
The Skip Registers | 01/01/70 00:00 |