??? 08/23/11 22:39 Modified: 08/23/11 22:43 Read: times |
#183443 - the story Responding to: ???'s previous message |
Basically: The person who designed the crossbar solution was not having a good day. Or maybe was at his/her peak performance but would have been better placed at a different position in the staff hierarchy. The concept might have sounded slick when originally thought about, but having the enabling/disabling of one peripherial move the pin allocations for multiple other peripherials is a very hurtful design choice. Real life products have a tendancy to change during their life time.
A very, very good processor design would have had a full crossbar switch, allow new peripherials to be used without affecting any other assignments. A "high up" Cygnal (it was in those days) person told me: "A full, "desirable" crossbar was in the first SILabs chip prototype. It turned out to take 7/8 of a too large die. Thus the "hurtful" crossbar was implemented." the crossbar as is is not that big a deal if you know what you are doing i.e. not your first experience with it. I, today, if there is space, will allocate a few unused devices in the prototype crossbar to have some "shuffle room" Erik |
Topic | Author | Date |
C8051F120 SPI0 and UART1 | 01/01/70 00:00 | |
priority crossbar | 01/01/70 00:00 | |
Caution on Using SiLabs Parts | 01/01/70 00:00 | |
Hurtful choice | 01/01/70 00:00 | |
the story | 01/01/70 00:00 | |
Best is normally in the middle | 01/01/70 00:00 | |
TY | 01/01/70 00:00 | |
I meant port pins | 01/01/70 00:00 | |
The Skip Registers | 01/01/70 00:00 |