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???
08/05/11 14:15
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#183220 - Much to a real UART
Responding to: ???'s previous message
The majority of real UART requires 16 times the baudrate as input clock, to get better at handling noise. Some few UART just runs at 8 times the baudrate.

So why 16 times the baudrate?

First off, they sample for the start bit, and a high sampling rate means they will be better synchronized - important if there is a baudrate mismatch (more common earlier when everything didn't have a high-quality crystal to generate the frequency).

Next thing is that they take multiple samples of the start bit, to avoid capturing a byte for a very short pulse.

Next thing is that they normally takes 3 samples in the middle of each bit, and use majority vote to decide if it's a high or low bit. This improves the noise immunity.

Making sure that the three samples are in the middle of the bit (not too close to start or end of bit) makes sure that a slight baudrate error will not result in one of the samples reaching the previous or next bit.

Finally, they perform a careful check for the stip bit(s), which will spot two error causes:
- a hung signal line constantly generating the start condition.
- transfer synchronized to the middle of a byte transfer, in which case a data bit is incorrectly assumed as a start bit. Then you normally get following start bit or random data bits where the stop bit(s) should have been.

If you do send your bytes with a short, or none, pause between stop bits and next start bit, and the data have specific content, then you could get an UART to continuously error-sample the data. The use of dual stop bits reduces this probability by improving the chance to detect a framing error - but obviously fails with that depending on transmitted bytes. This is also the reason why packed-based communication normally have a pause of more than one full character transfer time between packets - then the next packet will start correctly synchronized.

In the end, a single-sampling software UART will have much worse behaviour than a hardware UART with the exception that it might possibly be quicker to synchronize with start bits.

List of 30 messages in thread
TopicAuthorDate
bit banging program touble            01/01/70 00:00      
   why?            01/01/70 00:00      
      i need a second serial port            01/01/70 00:00      
         something like this , without any warranty :            01/01/70 00:00      
         a good start would be ...            01/01/70 00:00      
            only 3 'U's are commingout of 100            01/01/70 00:00      
               Separate the characters and look with scope            01/01/70 00:00      
                  finally it worked            01/01/70 00:00      
                     uart receiver in software            01/01/70 00:00      
   No I/O or No Timing            01/01/70 00:00      
      "No I/O or No Timing"            01/01/70 00:00      
   Someday you will learn...            01/01/70 00:00      
      this isnt the actual code            01/01/70 00:00      
         Well then another lesson to learn...            01/01/70 00:00      
   Assembler Manual will help you            01/01/70 00:00      
      assembler manual?            01/01/70 00:00      
   Data is 8 Bit??            01/01/70 00:00      
   Bit width timing and timer TH0,TL0 Values            01/01/70 00:00      
      checked values for TH0 and TL0            01/01/70 00:00      
         keil baud rate Calculator not for bit bang            01/01/70 00:00      
   LSB first            01/01/70 00:00      
   now reception....            01/01/70 00:00      
      1) din = din >> 1            01/01/70 00:00      
         working at 1200 baud            01/01/70 00:00      
            delayRS()            01/01/70 00:00      
               why do i have to sample stop bit            01/01/70 00:00      
                  Need not, but should            01/01/70 00:00      
                  because            01/01/70 00:00      
                     Much to a real UART            01/01/70 00:00      
                  1.5 bit delay            01/01/70 00:00      

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