| ??? 03/15/11 18:27 Read: times |
#181594 - SPI vs parallel Responding to: ???'s previous message |
Using SPI flash complicates things in that I need to hang an SPI port off of the micro's memory interface. The Actel core does have provisions for adding wait states so the interface could be somewhat transparent.
The other obvious solution is to read the flash into RAM at start-up, and have the micro execute out of that. 24 blocks, each 4608 bits, of dual-ported RAM makes this somewhat simple. Of course if I'm shadowing, it probably makes sense to keep the program size small (8k bytes or less) and embed the firmware into FPGA RAM and be done with it. Now if Actel has something similar to Xilinx' data2mem program, that'd be swell for debug, and once the code is locked down, it can be included in the FPGA configuration. -a |
| Topic | Author | Date |
| 8051 core in Actel ProASIC3L FPGA | 01/01/70 00:00 | |
| NOR Flash | 01/01/70 00:00 | |
| re: NOR | 01/01/70 00:00 | |
| PITA | 01/01/70 00:00 | |
| SPI vs parallel | 01/01/70 00:00 | |
| Using FPGA Resources | 01/01/70 00:00 | |
| Better with multiple, smaller, pages than one large. | 01/01/70 00:00 | |
FPGA rom | 01/01/70 00:00 | |
| What Triscend did | 01/01/70 00:00 |