| ??? 03/15/11 17:08 Read: times |
#181590 - NOR Flash Responding to: ???'s previous message |
Is that external NOR Flash a parallel bus inteface part or a SPI Flash type thing?
If it is parallel so that you have the option of running the MCU code directly fetching from the part then you have two options. a) Choose a NOR Flash type that has the ability to allow reading from one sector while another is being erased/programmed. b) Write your Flash block write/erase routine as a small block of code that you can relocate to RAM to run it for the duration of the flash erase routine. If you are using a serial (SPI type) Flash then you have two different options. 1) Design a hardware state machine that initially copies a boot block from the SPI Flash to a section of RAM and then release the MCU core from reset to run that code. 2) Design an interface that caches small pages of the SPI flash into FPGA RAM and permits the MCU to execute through this cache mechanism as a sort of "direct execute from serial flash". Michael Karas |
| Topic | Author | Date |
| 8051 core in Actel ProASIC3L FPGA | 01/01/70 00:00 | |
| NOR Flash | 01/01/70 00:00 | |
| re: NOR | 01/01/70 00:00 | |
| PITA | 01/01/70 00:00 | |
| SPI vs parallel | 01/01/70 00:00 | |
| Using FPGA Resources | 01/01/70 00:00 | |
| Better with multiple, smaller, pages than one large. | 01/01/70 00:00 | |
FPGA rom | 01/01/70 00:00 | |
| What Triscend did | 01/01/70 00:00 |