It would seem that nobody wants to recognize that the rise and fall time of Vcc are critical in their MCU's behavior. Some spec's are clear enough to reveal that the minimal reset interval, i.e. pulse-width of active RESET, is 24 oscillator cycles, for those MCU's that use the OSC/12 system clock, unless otherwise specified. That's VERY far from the "weeks-long" rise and fall of RESET when provided by the classic 10uF cap to Vcc and 8k2 resistor to GND. The problem that this long RESET solves is with the oscillator startup, which, from my own observations is seldom a problem with insufficiently rapid risetime of Vcc.

Having observed anomalous behavior during slow rise and fall of Vcc, particularly during the decay after power-off, I'd recommend no more than 50 us risetime and no more than 250 us fall time on Vcc. This means that some significant effort has to go into minimizing the bulk capacitance between Vcc and Gnd. If you use the on-chip crystal oscillator, it does require attention to the rise-time in order to ensure proper oscillator startup, and it's not a bad idea to stop the thing forcibly at brownout. Further, I'd recommend one ensure a sharp (<100ns) rise and fall time on RESET, and not the "weeks-long" slope on that 10 uF to Vcc cap with an 8k2 resistor to GND that so many manufacturers recommend.

Now, what YOU choose to do is up to you. Keep in mind, however, that the commonly advertised RC reset was developed before FLASH meory, before popuoar low-power CMOS technology MCU's, and before switching power supplies became popular for small applications. I find it utterly peculiar that so many datasheets still promote the old 1978 RESET circuit. A little arithmetic and a little study of the spec's will provide much more useful information.

RE