| ??? 02/02/09 21:35 Read: times |
#161962 - Timer counters connected to PLL Responding to: ???'s previous message |
I found an obscure note in the data sheet referencing the PLLCON register, and this alludes to your earlier post about the clock rate possibly being 1/12th of the core clock. The following quote seems to point in the same direction you had mentioned: Pg. 60 of the ADUC845 data sheet
"The default core clock is the PLL clock divided by 8 or 1.572864 MHz. The ADC clocks are also derived from the PLL clock. I haven't gone back to this problem yet and reworked the math, but I'm willing to bet there's a tight correlation here. Thanks for all your help |
| Topic | Author | Date |
| ADUC845 Timer2 Control Basics | 01/01/70 00:00 | |
| Well well... | 01/01/70 00:00 | |
| I'm guessing you already know.. | 01/01/70 00:00 | |
| Doesn't clarify why that value | 01/01/70 00:00 | |
| the absolute duration of one timer tick... | 01/01/70 00:00 | |
| not important, but what is | 01/01/70 00:00 | |
| The timer tutorial was not helpful | 01/01/70 00:00 | |
| It's the math that doesn't seem to work | 01/01/70 00:00 | |
| 321 Interrupts | 01/01/70 00:00 | |
| Experimental path probably best | 01/01/70 00:00 | |
| BTW - XLS Modeling | 01/01/70 00:00 | |
Timer counters connected to PLL | 01/01/70 00:00 |