Here is the whole case mathematically, if someone could explain what basic understanding I'm missing.

Frequency of core clock 12.58 MIPS
Clock offset at initialization 0x6700 = 26368
16 bit register max value = 65535
65535 - 26368 = 39167
So the timer register can only be incremented 39167 before each interrupt occurs. TH2-TL2 are incremented once per clock cycle.
12,580,000/39167 = ~321 which suggests to me that 321 interrupts should happen as the register will overflow and, as I currently understand it, the RCAP2L & RCAP2H values are restored into TL2 and TH2 respectively after each interrupt thus guaranteeing a consistent offset.

There is a comment in the sample code that is as follows(fyi an LED lights up at each interrupt):

//Flashed LED on P3.4 approx. every 20Hz

This comment seems to suggest only 20 interrupts per 12,580,000 clock cycles, which indicates 12.58M/20 = 629,000 cycles is occurring between each overflow. Even if these values are divided by 2 (to accomodate a clock cycle being 2 for high/low transition) the numbers don't work out. See the data sheet starting on pg. 75

http://www.analog.com/static/imported-files/Data_Sheets/ADUC845_847_848.pdf

precise understanding and control of the timer in this application is important. What am I misunderstanding here?