??? 01/16/09 07:53 Read: times |
#161549 - this is no definitive proof Responding to: ???'s previous message |
Provided that "restart" means jump to 0 and then set all registers which can be set explicitly from software, if an ISR has exit through ret rather than reti, the symptomps would be the same - interrupts of the same priority are prevented from being executed as long as *internal* registers (not readable nor writable explicitly by program) indicate that an ISR of the same or higher priority is still being executed.
You might consider posting the extint 1 ISR here for public scrutiny, if it's not too long. There might be no visible problems there, though; it might be for example also a stack overflow problem (especially if all 4 ISRs might nest in each other, given they are all of different priority). JW |
Topic | Author | Date |
P87LPC764 External Interrupt1 failure | 01/01/70 00:00 | |
consider software problem | 01/01/70 00:00 | |
EXT int1 failure in LPC764 | 01/01/70 00:00 | |
Restarted how | 01/01/70 00:00 | |
this is no definitive proof | 01/01/70 00:00 | |
Ext int1 failure - LPC764 | 01/01/70 00:00 | |
what is flowed? | 01/01/70 00:00 | |
a comment on Jan's post | 01/01/70 00:00 | |
Yes, listen to Jan and Erik | 01/01/70 00:00 | |
Shall check on exit thro RET![]() | 01/01/70 00:00 |