| ??? 05/19/12 08:29 Read: times |
#187430 - It didnt work because Responding to: ???'s previous message |
VHDL doesn't allow ports with just outputs, same as it doesn't allow ports with just inputs.
Even with very simple examples its always best to still the code though some kind of simulator, and you can use the synthesis tools to show you how the code has been implemented.VHDL compilers are notorious for producing the most useless error messages in the entire history of the universe so don't rely on them to tell you whats going wrong. |
| Topic | Author | Date |
| verilog to vhdl | 01/01/70 00:00 | |
| Problem solved | 01/01/70 00:00 | |
| It didnt work because | 01/01/70 00:00 | |
| Check out this site | 01/01/70 00:00 | |
| Verilog | 01/01/70 00:00 | |
| Why not? | 01/01/70 00:00 | |
employers!!! | 01/01/70 00:00 |