I don't know why a simple VHDL program to turn on a single LED on pin31 didnt't work which is this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mled is
    Port ( LED2 : out  STD_LOGIC);
end mled;

architecture Behavioral of mled is
    begin
    LED2 <= '1';
end Behavioral;


 

while a slightly more complex traffic light program worked :

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity TRAFFIC is
    Port ( My_clk       : in  STD_LOGIC;
           Red_light    : out STD_LOGIC;
           Yellow_light : out STD_LOGIC;
           Green_light  : out STD_LOGIC);
end TRAFFIC;

architecture behavior of traffic is
	signal my_counter     : std_logic_vector (4 downto 0);
	signal my_state       : std_logic_vector (2 downto 0);
	constant RED_STATE    : std_logic_vector (2 downto 0) := "100";
	constant YELLOW_STATE : std_logic_vector (2 downto 0) := "010";
	constant GREEN_STATE  : std_logic_vector (2 downto 0) := "001";

	begin
    Red_light <= my_state(2);
    Yellow_light <= my_state(1);
    Green_light <= my_state(0);
    process
		begin
		wait until My_clk'Event and My_clk = '1';
		case my_state is
		
		when GREEN_STATE =>
		    my_counter <= my_counter + 1;
		    if my_counter = "11110" then 
		        my_state <= YELLOW_STATE;
		    end if;
			 
		when YELLOW_STATE =>
			my_counter <= my_counter + 1;
			if my_counter = "11111" then 
				my_state <= GREEN_STATE;
			end if;

		when RED_STATE =>
			if my_counter < "11110" then 
				my_counter <= my_counter + 1;
			else
				my_state <= GREEN_STATE;
				my_counter <= "00000";
			end if;
		
		when others => my_state <= RED_STATE;
			my_counter <= "00000";
		end case;
		end process;
end Behavior;
 

I will attempt the verilog translation by writing it in VHDL from scratch as an excercize.