The NXP LPC1850FET256 and the NXP LPC4350FET256 look like interesting devices. It appears for both families that in order to get the USB 2.0 High Speed to work on both of the USB ports that one of them will require an external PHY. These devices do not have internal FLASH for program storage and instead are typically meant to have code read out of a SPI Flash part. Now whilst the parts do claim to support direct code execution from the SPI Flash it would be at decreased performance since in that mode you can apparently support only a 40MBytes/sec rate from this interface - and it looks to me that this rate is supported when all four of its I/O lanes are used in parallel from parts that support this capability. If operating with legacy SPI Flash parts with just a single pair of MOSI and MISO lines then the direct execution mode is going to be much slower.

It is interesting to note that the '4350 part will have two processing cores. One a Cortex-M4 and the other a Cortex-M0. Both part families are still in development status and so not available for production type purchases at this time.

Michael Karas