Yes, every technology does have resistances, capacitances, ...

So every transistor type fights its own internal capacitances.
And every transistor type also fights load capacitances - traces, more transistors, ...
Ande every design suffers from leak currents - output stage leaks and input stage leaks.
And circuit designs may suffer from large shorts to GND (such as both transistors in a totem design being partially open at the same time during the switching stage, giving faster switching than if one transistor closes before the other opens)

But the change of technology have greatly changed the proportions between these different sources of losses, making it very much a question of R and C. We have Oncle Miller involved for the transistors themselves, affecting the switching speed and efficiency of the transistor, and we have loads that draws almost zero static current but needs to be charged/discharged.

So in the end, it's not so much an artifact but something that gets clearly visible as a consequence of the very low static leaks no longer masking the losses caused by capacitances (and the series resistances the charge/discharge currents have to run through). The Miller effect isn't new to CMOS or FET. As Erik notes, it existed with valves/tubes. But the change in static current is drastically changed since bipolar and NMOS which is the reason for our completely new look at fan-in/fan-out. We don't care about static fan-in/fan-out anymore, but cares about the transition speed. How the bandwidth of the signal gets affected by the number of inputs, instead of how the staady-state voltage gets affected by the large static currents of the inputs.

It is quite common that behaviour of different circuits depends on many factors, and that technological improvements may greatly change the proportions between these factors. When one parameter gets greatly improved, we take a couple of steps forward but will instead find other parameters that will represent the new main limitations.

The reason I did write "CMOS (and similar)" in my first post was just that the the phenomenon is not new, but the transition to CMOS from NMOS has greatly changed the weight of different parameters, making the steady-state losses drastically lower, making the other losses much more noticeable. Bipolar constructs also suffers from the Miller effect, and also have capacitive loads to charge through wires and transistors with inherrent resistances. I do not think the OP was expected to discuss the internals of different transistors, but should have picked up a basic understanding of dynamic and steady state from the teacher. It would be a very strange electronic course to not talk about this.

By the way - a quite good discussion of Miller capacitance relating to FET switch transistors can be found in page 9 to 11 of this "quick course" of power MOSFET:
http://www.irf.com/technical...mosfet.pdf