But did you notice what I did write?

The small transistor sizes makes the transistor count irrelevant.
And the chip area is greatly affected by things like bonding pads, big input/output transistors etc.

So while the chip itself isn't free, the "dynamic cost" of extra transistors is practically zero. And that is a reason why you may in some situations find the same silicon in multiple different processors. All that differs may be an identifier and potentially some enabling transistors - and the fact that maybe some I/O signals aren't bonded to any pin.

With small core geometries, a core transistor can not interface with a processor pin. Not only is it too sensitive to ESD. It also lacks the driving capabilities needed. So you have special input/output transistors with way larger geometries. And you may potentially have layers of intermediate transistors just because a tiny core transistor can't recharge the capacitances of the huge output transistor fast enough.

So while 130nm may require about 1V logic levels because of breakdown voltages, the processor can generate 1V internally. So the core has a lower breakdown voltage. But at the same time, the smaller feature sizes results in lower induced voltages if affecting the chip with a magnetic field.

So much of the issues you mention with smaller technologies are only applicable for "slightly" smaller geometries - scale downs where the manufacturer have made a general reduction of feature sizes. When you continue with the scaling, you stop trying to make the interface layer smaller. You still want same drive currents and same ESD survivability. You just want the computational stages scaled down to allow them to run faster and at the same time consume less power.

You worry a lot about smaller geometries, taking mobile phones and toys as examples. But I think you are missing the important fact that routers, switchers, cellular networks, ... are embedded non-toy products in active use. And definitely walking the route to smaller geometries because the cost of operations stands for a huge percentage of the total lifetime costs.

Smaller flash does not mean shorter retention times. Retention times are just a factor of number of electrons in relation to the leakage of electrons. A cell with a million electrons that leaks 10k electrons/year does not have any better retention than a cell with 10k electrons that leaks 100 electrons/year.

In some situations, you can show that a smaller total count of electrons can make an individual cell more sensitive to radiation. But on the other hand, a smaller geometry means that a specific cell is harder to hit. And smaller geometry allows the chip to have better ECC wich means that it can continue to produce correct data with a significant number of toggled cells. Older chips with less ECC capabilities - or maybe only parity or checksumming - may have a bit robuster individual cells but can still end up way worse if considering number of bit errors/year.

Next thing is that many of todays faster processors (even quite small microcontrollers) have received ECC-corrected internal busses, thanks to the small cost of adding extra transistors. And the high speed the tranistors can operate at when close together with miniscule signal path lenghts.

A big question is: how to define "mature"? Remember that many process technologies have been in use for many years in other areas even if there hasn't existed fab capacity to use it for smaller microcontrollers. With $1,000,000,000 and more for a single fab, it really does take some time until the new process technologies trickles down to the lower end of the embedded world. 10-15 years ago, companies constantly run two fabs. Building/calibrating one fab while producing in the other. After switching, the older fab got scrapped and it was time to replace everything. Today, that older fab is still so massively expensive/valuable that it isn't scrapped but reused for smaller product lines. So it is a bit simplistic to call this left-over technology immature.