1,
R-pull-up not too low in value - as to draw excessive current when internal open drain FET pulls low..

2,
R-pull-up not too low in value as to exceed Logic low thresholds when internal open drain FET pulls low.

3,
R-pull-up not too high other wise RC time constant is too long to effect bit timing period.... Where C is bus capacitance.


Hence - 3 three requirements to help select a "range" of acceptable R-pull-up values.

See page 42 of
http://www.nxp.com/acrobat_d...0204_3.pdf
for an example

Joe