I work where we design server main boards. The high speed busses must be length matched if there is a hope of getting things that run up into the 100's of megahertz (or even gigahertz) to work properly. The design teams always include a group of people that model and simulate every bus layout artwork to ensure that the signal integrity rules are met. This set of rules includes specification of the maximum allowable skew for signals on a parallel path to arrive at the destination. The propagation delay differential from path to path is compensated by making the trace lines in the bus all the same length (within the allowable skew).

Many high speed paths use differential pairs to transfer signals for the bus. These pairs must be length matched to about 0.1 inch and in some cases less than 50 mils (0.05 inch). When a parallel bus includes these differential pairs it is not uncommon to see the squiggly lines include pairs with carefully controlled spacing between each of the two lines in the pair to control impedance all the way from source to destination.

It has been found that certain manufacturing tolerances of making the PC board fabs leads to distortion of the differential pair line impedance. For this reason it is common to see several long diff pairs routed on the board that connects to nothing but test points. This is used to test the differential pair trace impedance during the board fabrication process to ensure that the board will meet specs. Some boards even have special pads at the ends of these traces (and two adjacent guide holes) to permit a test probe with two pogo-pins to be inserted such that the trace impedance achieved on a fab can be quickly checked without having to use a full bed of nails test fixture.

Here are some links to learn about just how fast these busses are getting:
http://www.intel.com/pressroom...corp_b.htm
http://en.wikipedia.org/wiki/Inte...terconnect

Here is a link that describes considerations that come into play when making PC boards with these high speed busses. The design rules used for differential bus squiggly lines must now take into account how those busses cross the FR4 weave in the PC board material.
http://www.altera.com/technolog...apr_1.html

Michael Karas