This is a parallel I/O device, so it depends on what you mean, Kai.

Writing a bit takes just as long as writing a byte. Writing to different ports requires writing to different addresses, so the access time has to be increased to include T(ar). The write-recovery time is an issue at times, too, though I haven't found a precise definition. Normally this is the time that has to elapse before the port is written again. That would then be the rate-determining step, leaving the write cycle + recovery time at about 320 ns per byte. If, then one were to write to all three ports, it would require somewhat less time, since the write-recovery time applies only to one port. Writing to three ports in succession would consume 360 ns, since the write-recovery times overlap. That would give you 24 bits in 360 ns if you use a 120 ns write-cycle. A lot would depend on the bus-side waveform of the sort of MCU you're using if it's an external memory bus cycle, as the actual time at which the nWR pulse becomes active is a factor.

So ...
360 ns/cycle; 24bits/cycle; 1923 cycles/half-millisecond ... implies 46152 bits per half-millisecond, which is actually plenty. That does not, however, take into account fetching and blocking the data, pointer maintenance, or any other overhead that must be accomplished along the way if the rate is sustained. If one uses a port-mapped interface, those operations can be interleaved between the control signal writes, but that's not the case with memory-mapped I/O and bus-cycle stretching.

RE