I've done a couple of NAND flash controllers, and had I had my own way, I wouldn't have done them the way I did them. (Don't ask.)

Instead of using an 8052, I'd embed a Xilinx PicoBlaze in the FPGA. No need for another component.

The reason for using the 2k buffers (plenty of RAM in the FPGA) is that the larger NAND flashes have a page size of 2k bytes. (Smaller devices have 512-byte pages.) For writes, the host would simply fill the buffer with a pageful of data, and then write a "do the write" command, and the controller's embedded processor would go off and program that page. After the page program completes, the controller could then verify that the programming worked (reading back the page into the other buffer, then comparing the two buffers). Finally, when programming and verification are done, the controller can interrupt the host, indicating success or failure and that it's ready for the next page.

Similarly, for reads, the host can write a "do the read" command to the controller. The controller will then go off and read the page, stuffing the data into the read buffer. When the read is complete, the controller interrupts the host to say, "data ready, come and get it."

-a