Eric,

Thanks for your reply.

It's not clear to me that this is the problem. Based on the AT89C51RC2 datasheet (unless I've misread it) it sounds as if the device comes up with the X2 bit(s) cleared, which would put it into 8XC51 operational mode. See below. Note: The X2/CPU Clock bit is in the CKCON0 reg and is s/w programmable. The HSB X2 bit has to be set at FLASH programming time (Hmmmm...since I'm using ext. FLASH at the moment, I wonder if that might be an issue?)

Maybe I'm missing something else here.

Cheers...Steph

X2

CPU Clock
Cleared to select 12 clock periods per machine cycle (STD, X1 mode) for CPU
and all the peripherals. Set to select 6 clock periods per machine cycle (X2
mode) and to enable the individual peripherals�X2� bits. Programmed by
hardware after Power-up regarding Hardware Security Byte (HSB), Default
setting, X2 is cleared.

This is the info about the HSB (mentioned in the X2/CPU Clock above).....

X2 Mode
Programmed to force X2 mode (6 clocks per instruction) after reset.
Unprogrammed to force X1 mode, Standard Mode, after reset (Default).