| ??? 12/13/11 22:27 Read: times |
#185082 - silabs with cache Responding to: ???'s previous message |
Thanks for the comment, Frieder.
I went to the Silabs datasheets and I think I know how it works, but I need to have this confirmed. So, normally, in the 25MHz parts, the unconditional jumps take some cycles, say 3 for SJMP or 4 for LJMP; and the conditionals appear to take a different number of cycles depending on whether the jump is or is not taken, say 2/3 for JC and 3/4 for JB. Now this means, that if there is a cache miss, the instruction may take 4 cycles more to fetch the word containing the target of the jump. That happens only when the jump is taken with the conditionals, so I should write say 3/4+4 for JB, correct? My problem is, that the datasheet mentions also less-than-four-cycle cache-miss penalties. How comes? I couldn't really find the explanation in the datasheet, and did not dig deeper back then (nor now). Can anybody explain these details for the >25MHz Silabs's? Thanks. Jan |
| Topic | Author | Date |
| '51 derivatives cycle comparison table updated | 01/01/70 00:00 | |
| above about 40 Mhz devices may need extra cycles | 01/01/70 00:00 | |
| silabs with cache | 01/01/70 00:00 | |
| Ok, a SILabs cache lesson | 01/01/70 00:00 | |
| Bytes | 01/01/70 00:00 | |
| ecc? | 01/01/70 00:00 | |
| not the cookies | 01/01/70 00:00 | |
| Washed? | 01/01/70 00:00 | |
| am I as has happened before ... | 01/01/70 00:00 | |
| Is that how it's spelled? | 01/01/70 00:00 | |
| re: Washed? | 01/01/70 00:00 | |
| jump cache miss penalty | 01/01/70 00:00 | |
| clarifications | 01/01/70 00:00 | |
| no cache for 50MHz | 01/01/70 00:00 | |
| surely not all | 01/01/70 00:00 | |
| you missed a word | 01/01/70 00:00 | |
| more update | 01/01/70 00:00 | |
| Table suggestions | 01/01/70 00:00 | |
Updated MC51 supports Cycle Define | 01/01/70 00:00 |