| ??? 12/12/11 22:11 Read: times |
#185079 - above about 40 Mhz devices may need extra cycles Responding to: ???'s previous message |
Hi Jan,
thanks for the table!) Devices with high core frequency (c8051f120 and the likes) might need extra cycles due to instructions being or not being in cache (or prefetch). (Or instructions which span more than one byte being or not being aligned to flash memory bus width of 16/32 bit). Not sure how this could be represented in a table. Eventually footnotes would be fine? Greetings, Frieder |
| Topic | Author | Date |
| '51 derivatives cycle comparison table updated | 01/01/70 00:00 | |
| above about 40 Mhz devices may need extra cycles | 01/01/70 00:00 | |
| silabs with cache | 01/01/70 00:00 | |
| Ok, a SILabs cache lesson | 01/01/70 00:00 | |
| Bytes | 01/01/70 00:00 | |
| ecc? | 01/01/70 00:00 | |
| not the cookies | 01/01/70 00:00 | |
| Washed? | 01/01/70 00:00 | |
| am I as has happened before ... | 01/01/70 00:00 | |
| Is that how it's spelled? | 01/01/70 00:00 | |
| re: Washed? | 01/01/70 00:00 | |
| jump cache miss penalty | 01/01/70 00:00 | |
| clarifications | 01/01/70 00:00 | |
| no cache for 50MHz | 01/01/70 00:00 | |
| surely not all | 01/01/70 00:00 | |
| you missed a word | 01/01/70 00:00 | |
| more update | 01/01/70 00:00 | |
| Table suggestions | 01/01/70 00:00 | |
Updated MC51 supports Cycle Define | 01/01/70 00:00 |