I agree that as long as manufacturers don't provide better reset circuits than the old classic, we'll see nothing better from them.

The problem lies in the poorly specified relationship between rise and fall time of Vcc, the oscillator startup time, and the MCU behavior during the interval between oscillator startup and proper Vcc level while the RESET voltage is still out of specified limits.

From what I've gathered, one specified reset characteristic is that the MCU requires a period of 24 oscillator cycles to "get its self together" during active RESET, so that defines a minimal reset pulse width. I've seen no comparable characterization that's applicable to the one-clockers, two-clockers, etc.

Flash memories, NVRAM, etc, that are expected to be nonvolatile don't seem to have compatible spec's with the RESET voltage and Vcc levels specified for some 805x's (I haven't seen all the spec's). Maxim/Dallas, just for example, specifies the write-inhibit levels for their NVRAM differently than they specify them for their MCU's, and also for their supervisor chips. This can lead to a lot of confusion, and makes it hard to guess which of their thresholds should be tweaked to make these devices play together.

I've observed runaway write behaviors on Maxim/Dallas, and other 805x's during active RESET during the decay of Vcc. One of these days, when I am able to locate the fixture in which I observed that (I moved a couple of years ago, and not everything has surfaced yet.) and I'll try to get a good "picture" of it doing exactly that.

If there are good spec's for the relationships between Vcc rise/fall, oscillator startup, and reset width, particularly for some of the newer, non-12-clockers, I'd be very interested.

RE