Murray,

To capture the low level --> tristate level signal will require that you add a pullup resistor to the tristate signal so that the detecting circuit has a reliable logic signal to work with. Without knowing a lot about the nature of the conditions that generate the transition to tristate of this signal it may necessary to buffer the transition to get a good logic edge to work with.

In addition, since your power down recovery signal for the AT89C51AC2 has to be a timed pulse (needed due to the fact that the MCU will not resume execution of instructions till after the the end of the pulse) you will need some timing circuit to generate this pulse timing.

You mention that you have next to no power budget left for providing power to an additional circuit. If you utilize some CMOS inverter circuit the power requirements will be very low and hardly noticeable to your power source.

You also mention that board space is at a premium. There are a number of choices for very small logic chip packages that are surface mount packages that take only a small amount of space. You should investigate the various "tiny logic" families offered by various manufacturers to see just how small these packages can be. Consider the logic type parts that have the "1G" and "2G" indicated within the name to as these will be one-gate and two-gate type packages to achieve the low pin count and small size.

Here is a proposed circuit that could meet these design constraints.



Michael Karas