This stuff is thoroughly documented.

Since the early days of 805x, people have ANDed nPS, nRD, and nWR in order to generate a common enable for access to external read/write memory. The result is that you can then build a battery-backed RAM memory, write to it in one context in which an internal program is "in charge" of what's going on in order to load the external memory, and then tie nEA low and assert RESET so that the internals of the 805x will "see" the state change of nEA and act on it. The result will be that whatever code resides in the external memory at 0x000 now becomes executable.

Fast-forward to 2010 or thereabouts, and you can use FRAM, which not only is readable at system speed but writeable as well, and you have something pretty simple to use.

Program a simple program into the MCU's internal program store, load the FRAM with whatever monitor, interpreter, or application you desire, then switch the nEA to low, and you have a system in which you are free to write to your program space, since it's combined with XRAM space. MOVX will write to it and read from it, and MOVC will read from it as you wish.

If you need to preserve the P2 outputs, you can even register them at the rising edge of ALE with a 74HC273. It's even possible to create inputs on P2 with more complex hardware, but probably not worth it for your current needs.

I've not tried it with the newer 805x MCU's, but it might even be possible, with the ones your using, to change the state of nEA in order to use internal code space as executable program space, but I'd be surprised to find that true. The original 805x's sampled nEA at a particular T-state after the falling edge of RESET, and latched the state of nEA until the next RESET.

As for combining XRAM and external code space, I've done that many times with BBRAM's. I've even done it with FRAM. One thing that you might even consider is using a really large FRAM so you can page the contents. I've found that you can generate another nybble of address by clocking a 4-bit counter on the falling edge of A15 during ALE. Another thing you can try is to register a few extra address bits on P2 as I described earlier, and use those as additional address bits.

While this is all well documented in history, it's not been documented by manufacturers of 805x chips. Too bad ...

RE