It wasn't uncommon for the ISP/ICP to still require the high voltage - whenever you connect a programming probe (serial or parallel) you may just as well supply 7V or 12V or whatever the chip might need. With the IAP, you got a solution where the system is intended to be self-programming, in which case external electronics to boost the voltage would represent board space and cost. I feel this was the main driving force for internal voltage boosts.

So basically, the IAP was the step when it became advantageous to incorporate the voltage boost inside the processor. With internal voltage boost, the ISP/ICP can also skip external high-voltage signals. A number of processors is using a SPI interface but running the interface while the reset is active for ISP/ICP prgramming. As long as external electronics using these pins are fine with the signals jumping up and down while the system is in reset mode, such a solution will not consume any processor pins.

One thing I am a bit unhappy about is why not all processors who have hardware - or internal boot loader - to perform the actual programming after receiving data serially doesn't have the serial protocol documented. This would greatly help people who design multiprocessor solutions - having just a single connector and then route new firmware to all the processors on the board. After all, not all embedded processors have enough memory (and internal design) that it is practical to have every processor run a full user-defined boot loader that can receive new software and perform IAP.