found an 8052 core (t51) and an asynchronous core (DLX) but not both together (assuming here that t51 would explicitly mention asynchronicity if it was asynchronous).

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http://www.opencores.org/projects?cat=10&lang=0&stage=0&lic=0http://

List of microprocessor projects at OpenCores.

http://www.opencores.org/project,t51

T51 mcu :: Overview

Name: t51
Development status: Stable

8052 compatible microcontroller core. Two different top levels: T8052: - Single cycle synchronous RAM/ROM - Wishbone bus interface for memory mapped peripherals T8032: - Wishbone bus interface A utility to create VHDL ROMs is also included. To create a ROM compatible with the 8052 core type: hex2rom [-b] inputfile.hex ROM52 13b8s > ROM52.vhd Leonardo Spectrum can infer the ROMs created with hex2rom to Xilinx block RAM. I have also modified the baud rate recognition of the BASIC-52 ROM to support the faster instruction timing. The modified BASIC-52 might also work with other high speed 8032 compatible cores such as the 80c320. Browse source code here. Download latest tarball here.


http://www.opencores.org/project,aspida

ASPIDA sync/async DLX Core :: Overview

Name: aspida
Development status: Stable

The ASPIDA project has implemented an asynchronous IP of the DLX Instruction Set Architecture (ISA) with incorporated support for ISA conversion so it can be easily converted to any RISC ISA. The DLX architecture, is well-supported by existing software development tools (compiler, assembler, loader, instruction set simulator and debugger).

The synchronous single-pipeline architecture, which is standard for the basic synchronous DLX implementations, is identical to the architecture of the asynchronous version. A suitable Open IP interface (WISHBONE) is embedded onto the processor to enable it to be integrated into any Open IP SOC system. In addition, the ASPIDA project issues a new Open IP interface standard based on asynchronous technology (CHAIN), and support for this new Open IP interface is also embedded onto the processor core.

Features

- Technology-portable processor core
- Fully-asynchronous core for low-power, low-EMI
- Industrial-quality testability (internal scan)
- WISHBONE interface
- Core includes additional novel asynchronous bus, CHAIN (CHip Area INterconnect)
- Targetted for ASIC EDA flows

Status

- Project is completed
- Fully Working FPGA Implementation is available on Xilinx Spartan 2E device
- ASIC Implementation completed and tested
- Download FAQ and all the sources and scripts from the project download section
- Visit our ASYNC group web page at http://www.ics.forth.gr/carv/async