... no centralized clock.

Richard,

This is a "school" in digital design, where, roughly, individual functional blocks are accompanied by a "validity" signal, which is guaranteed to toggle or get valid or indicate in whatever manner, that the outputs of that block are valid. The data are in this way passed from block to block; thus, the whole circuit assembled from such blocks needs no centralised clock.

The advantages might be in decreased noise (switching "spreads out" naturally), and decreased current consumption (roughly, circuits which are not involved for a certain operation, don't "see" any changing input, so they don't switch). There were once hopes in achieving higher speeds than with synchronous designs, but that mostly cannot be achieved in practice.

The major disadvantage is the increased complexity of the design.

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Maxim,

I know of 2 asynchronous '51 designs:

- Handshake Solutions' HT80C51 IP core. This is a small company devoted to spun off Philips some 5-8 years ago. One of your links is probably of that origin, the authors are said to be of Philips and the timeline matches. Chips with this core appear to be in production, although they won't say in which chips particularly they use it, just point out vaguely that it fits smartcards, especially the contactless ones (due to low power consumption). They have removed almost all traces of it from their website, so you must resort to google and internet archive to find its remnants.

- Lutonium, an academic project from Caltech, of roughly the same age, which appears to be more "proof of a concept" than a real design

There probably will be more. Google is your friend. I doubt you will find a complete ready-made VHDL, so you must most probably study the topic and come up with your own design.

JW