| ??? 08/09/09 14:43 Modified: 08/09/09 14:45 Read: times |
#168277 - That's what the datasheet tells... Responding to: ???'s previous message |
Joe said:
Please cfm the following statement is true, as per your vice versa statement.
The Vdd of the P89LPC935 should rise slower 2 mV/µs and fall slower than 50 mV/µs. That's what the datasheet tells, Joe. Joe said:
I have heard that if Vdd rises too slow (eg charging up the Vdd Cap) then the micro may fail to startup. That's also true. Joe said:
So is there a Vdd rise time "window" as well as a Vdd fall time "window"? Usually there is, but if the datasheet gives no minimum specification of rise and fall rate, then infinite long rise and fall times seem to be allowed. Well, a maximum rise rate of 2mV/µsec roughly translates to a rise time which must not be smaller than 1.65msec for a step from 0V to 3.3V, which is rather steep, isn't it? And a maximum fall rate of 50mV/µsec yields a fall time which must not be smaller than 66µsec for a step of 3.3V to 0V, which is also rather steep. So, these specifications should not restrict you too much. There are many reasons why the rise time should usually as fast as possible: 1. If you have a built-in Pierce oscillator, which isn't designed properly (too low transconductance of MOSFETs, poor crystal, wide ambient temperature range, etc.), then you need a steep Vcc ramp to make it start-up quickly. But usually it doesn't really make a difference whether the Vcc rise time is 100µsec, 1msec or even 10msec. It would make a difference if the rise time is in the 100msec range or even beyond. Micros not using this built-in Pierce oscillator might not have this restriction at all. 2. Widely recommended RC resets only work if the Vcc rise time is much smaller than the RC time constant. So, many manufacturers recommend a Vcc rise time of less than 10msec, only because otherwise their recommended RC reset wouldn't work, although their micro would start properly with much bigger Vcc rise times, if only a proper reset chip was used. 3. Certain micros, e.g. some from SILABS, have a strange power on and brown out detecting scheme, where the POR delay seems to be timed from the power on detetcion and not from exceeding of Vrst. And because the internal fabricated delays seem to cannot be made longer than a few milliseconds, a longer Vcc rise time than 1msec will cause the device to be released from reset before Vcc reaches the Vrst level. When using an external reset, on the other hand, this Vcc rise time restriction might not be longer valid at all. Kai |
| Topic | Author | Date |
| LPC764 Oscillator problems | 01/01/70 00:00 | |
| it is a known fact that .... | 01/01/70 00:00 | |
| Well known... | 01/01/70 00:00 | |
| See also here... | 01/01/70 00:00 | |
| one added comment | 01/01/70 00:00 | |
| LPC764 Vdd rise time | 01/01/70 00:00 | |
| Vice versa! | 01/01/70 00:00 | |
| Vdd rise time LPC935 | 01/01/70 00:00 | |
That's what the datasheet tells... | 01/01/70 00:00 |