| ??? 06/23/09 19:11 Read: times |
#166399 - that was clearly possible, I wonder why ... Responding to: ???'s previous message |
... the OP TWICE Would not do that.
anyhow re. the code If there is an interrupt coincidence there is a slight possibility that reloading the timers without stop/load/start will give an error of 256 counts. also I would do this #if TIMER_COUNT >=1 timer0... #endif #if TIMER_COUNT >=2 timer1... #endif ...... ...... Erik |
| Topic | Author | Date |
| Pseudo timers make programming delays easy. | 01/01/70 00:00 | |
| volatile + racing condition | 01/01/70 00:00 | |
| slow processors | 01/01/70 00:00 | |
| You beat me to it... | 01/01/70 00:00 | |
| Timers_0.1 available. | 01/01/70 00:00 | |
| SDCC | 01/01/70 00:00 | |
| ISR defining with SDCC | 01/01/70 00:00 | |
| oh, I just read it in the manual | 01/01/70 00:00 | |
| only conditionally, as #ifdef SDCC | 01/01/70 00:00 | |
| SDCC and ISRs | 01/01/70 00:00 | |
| Prototyping ISRs | 01/01/70 00:00 | |
| you can see it as if.... | 01/01/70 00:00 | |
| SDCC Quirk? | 01/01/70 00:00 | |
internals of SDCC | 01/01/70 00:00 | |
| duh | 01/01/70 00:00 | |
| Too quick | 01/01/70 00:00 | |
| I see something else... | 01/01/70 00:00 | |
| That helped. | 01/01/70 00:00 | |
| Oops! Timers_0.2 available. | 01/01/70 00:00 | |
| you persist | 01/01/70 00:00 | |
| Good idea! | 01/01/70 00:00 | |
| atomicity | 01/01/70 00:00 | |
| No | 01/01/70 00:00 | |
| I gladly, click on a link .... | 01/01/70 00:00 | |
| Direct link | 01/01/70 00:00 | |
| that was clearly possible, I wonder why ... | 01/01/70 00:00 | |
| one more thing, now we are digging deep | 01/01/70 00:00 |