I'm not really certain that this is how it's supposed to work, and it may not be identical from one manufacturer to another, but I've seen applications, long ago, that did what you apparently want to do. If you bear in mind that some P3 pins are used for external memory bus control, i.e. P3.7 and P3.6, and if you register the P0 (be sure to provide adequate pullups!) and P2 bits that you can't have doing random things during ALE=1 and beyond, then, from what I've observed, you can use those same ports for external memory-mapped I/O. It seems, from documentation, that the high address byte persists on P2 during the external memory access cycle, then reverts to P2 latch content. P0 is the data bus during such cycles, so it has to maintain that function until the end of active nRD, nWR, or nPSEN. The port latch content should be valid on the next rising edge of ALE, though it's not clearly depicted on any timing diagram I can recall.

Unfortunately, I've not been able to get a precise reading on just exactly how this supposed to work from some chip-manufacturers, notably Maxim's DS89C4x0, since they have some unique address multiplexing modes available that aren't shared by other chip makers.

Many relatively recent MCU's don't generate ALE unless an external memory cycle is in progress. From that one can, I believe, safely deduce that the port latch values are what one can reasonably expect to "see" on those port pins. I'd conclude from that, that what will appear on those pins between the rising edge of ALE and the rising edge of one of (nPSEN, nWR, or nRD) will be external bus information, while port latch data should appear during the remaining time.

If you map your external ADC into external address space, you should have no need to bit-bang nRD and nWR. You have to register output bits with positive-edge triggered registers e.g. 74HCT273 on the rising edge of ALE in order to ensure that your P2 outputs are held stabile during external memory bus cycles. If you do that, you can decode external addresses for control functions for which you might otherwise have to use port bits, control of which is monentarily lost during external bus cycles. A 74HCT133 will easily detect the top 16 locations in memory space when fed the top 12 addresses and the NAND of nWR and nRD. One of those could be a control register. Parallel I/O in that range will be as fast as the MCU can go.

RE