With AC logic, the propogation delays are generally specified with a significant capacitive load, as that's what they often drive. If you build a simple circuit with little capacitive loading, you'll find the prop-delays are closer to the specified minima, rather than the 40 or 50 pf load they specify. Look at the datasheets from Fairchild, for example. The prop-delay I've seen on a 74AC86 has been closer 3 ns in my obervation, rather than the maximum shown in the sheet. Further, the clock-to-Q for the AC74 is close to 4 ns. I don't recall whether I mentioned that the output of that circuit is the output of the XOR. The first transition, BTW, may be different from the rest of them, but each one after that should reflect only the Clock-to-Q of the 'AC74, as the delay in the XOR remains a constant.

If I feed a 1 kHz square wave to that xor clocking DFF I described, you get a very nearly 5 ns pulse every half-millisecond. That circuit, BTW, is an edge detector, not a fequency doubler, as it reflects the input signal's duty cycle. It simply produces a positive transition for each transition of the input signal.

RE