This sort of project can be quite a lot of fun. In my experience you have to put quite a lot of thought into how the functionality is partitioned and on how you are going to handle inter-processor communication. You would probably want to hang all your processors on a bus of some sort, and bus throughput can quickly become a bottleneck. If you plan to have multiple bus masters then you need to decide how you resolve bus ownership. SPI will be a real handicap, so I would seriously consider looking at CAN bus.

An alternative to a shared high speed bus is to use point-to-point links (as promoted by the old Transputer). You would arrange your processors in a grid and each processor would have a link to its nearest neighbour, often thought of in terms of North, East, South and West. Not many processors have four UARTs, so this can be a deal breaker.