Hmmmm ... this looks as though it's 'C' code. Have you measured or calculated how long it takes the resulting binary code to execute? There are precise timing restrictions on the successive writes to TA.

the user guide exhorts the user to do the following.
1. Make sure the FBUSY bit is 1 to indicate flash MMU is idle.
2. Write 0Bh to the FCNTL register using the timed access sequence.
3. Write address_MSB to the FDATA register.
4. Write address_LSB to the FDATA register.
5. Write data_value to the FDATA register.
6. Make sure the FBUSY bit is 0 to indicate programming has started.
7. Wait for FBUSY bit to return to 1 to indicate end of programming operation.
8. Make sure FERR is 0 to indicate no programming error.

Timed access must be within three machine cycles: (from the datasheet)
Before these bits can be altered, the processor must execute the timed-access sequence. This sequence consists of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three machine cycles.

You might want to verify that this is happening as scheduled. I'm not sure how you do this without using different code that produces timing markers, which, of course, could alter the timing. I've got no idea at all what the compiler you're using does with this. Perhaps you should write your code in ASM.

RE