| ??? 01/20/08 22:19 Read: times |
#149783 - re: Xilinx BRAM with async read Responding to: ???'s previous message |
On Spartan 3 block RAMs, inputs (address, write data and enable) are synchronous to the port's clock. The outputs are not syncrhonous in the sense that the output data are valid a clock-to-out time after the clock (no pipeline).
-a |
| Topic | Author | Date |
| Xilinx block RAM with asynchronous read? | 01/01/70 00:00 | |
re: Xilinx BRAM with async read | 01/01/70 00:00 |