The LA is basically nothing else just a sequencer which generates successive addresses and a memory where the data are stored. You can try to do a simple loop like:

Grab:   
        MOV  A,P1
        MOVX @DPTR,A
        INC  DPTR
        MOV  A,DPH
        CJNE A,#HIGH(MEM_END),Grab

(of course after proper initialisation of DPTR) and fill up an external memory with 8-bit data attached on port P1. Later you can transfer it to PC and process further. This example reaches a whopping 140ksamples/s on the vanilla 8051 at 12MHz, but on faster '51 clones you could possibly achieve above 2Msamples/s (although you need much more to actually see 0.5us wide pulses - at least 5Msamples or better), especially if you unroll the loop and use features of the faster clones such as autoincremented DPTR (for features of fast clones see e.g. the overview at my 8052.com homepage). However, for faster sampling rates you will need to implement a separate logic (today often implemented in CPLD or FPGA) which will do the fast address sequencing, and use a fast memory. I am somewhat involved in an amateur LA construction ("miniLA") published at http://minila.sf.net (see also the links given there); and I am also preparing a simpler construction ("pikoLA"), 16 bits at 66 MSamples/s, controlled by - surprise, surprise - '51... (coming in December... hopefully).

Jan Waclawek