The fully software simulations of which I speak are whole chip logic level simulations that run with a complex behavioral model wrapped around it that acts like a real "rest of system" to exercise the chip logic just as it would in a real system powering up, going through resets, handling sleep states if applicable, transferring data around etc. etc. etc.

In the full chip simulation the 8051 core we use is instantiated just like any other IP block and gets treated just like a full hardware entity. The ROM that my firmware goes into is initialized into the simulation model as a big hardware array and accessed just like the 8051 code memory. The 8051 core used is a 1 & 2 clocks per cycle design. It is not like the old original x12 8051s/8052s of yesteryear. And it runs fast!!

Testing the software gets debugged looking at the waveforms that get generated out of the simulation so it is fairly tedious. Not at all dissimilar to debugging an embedded system that had a logic analyzer connected up to its address, data and control line busses.

I have to reserve comment on the ROM technology and how it gets applied as it is proprietary.

Note that there is a whole array of emulation testing done as well where the chip RTL design gets synthesized and mapped to these very large (and very expensive) FPGA boards that are able to test out the design too. These systems are generally used as the simulations get large sections proven out and then the emulation FPGAs are used to increase testing speed about 200-500X (still only effectively clocking the logic design in real time at about 0.5 to 1 MHz). The emulation testing focuses on tests where it would take several weeks to a month to run an equivalent simulation run.

In emulation runs on the FPGA boards my 8051 firmware still runs just like it would against the real hardware design. Debugging can be similar but the FPGA systems are generally not used to capture states of every node in the system at each sample period because it takes way too long to read all that data out of the FPGA boards and write it to disk. But if a design problem is noted the model can be rebuilt with as many probing points inserted as needed to focus on the issue at hand and then re-run the test with full state capture on those probe points.

This is all very interesting but not really all that unique to Intel. What is Intel is the amount of resources applied to getting the design as right as possible at first silicon. With the millions it costs to run a design through to that first testable silicon we do everything possible to assure success without re-spins of the design. Since every new Intel chip tends to be on the bleeding edge of process technology the main issues that come up at first silicon will be things that change between how the software models predict and what the silicon actually produces. For as complex as the chips are these days and the billions of transistors involved it is awesome that a new powered on chip may only see a couple of actual logic flaws.

Michael Karas