FSK does not have to be a 2::1 frequency shift to represent the bits encoding. I implemented an FSK transmit and receive scheme once where the frequencies were low enough (about 2.2 KHz) that I was able to use the Timer 2 to interrupt on every positive and negative edge and capture the width of each pulse. A relatively straight forward state machine keyed off the pulse catching interrupts would support states to count 1's and 0's, detect sync patterns, frame bytes, and manage a packet accumulation at the highest levels of the protocol. In the MCU that I used for that project the Timer 2 input had an external XOR gate that was controlled by another port pin output to permit the interrupt routine to control whether the next interrupt would occur on the positive or negative edge of the incoming signal.

You mention sine wave signalling. In that design the low level signal from the FSK signalling wire was coupled to/from the wire through a small 1::1 coupling transformer to provide DC blocking. On the receive side of things the signal was amplified with a nominal gain via an opamp and then fed into a comparator circuit with hysteresis. This converted the input signal to a square wave that fed to the XOR gate feeding the T2 input pin. On the transmit side the drive signal from the MCU was the T2 output as a square wave. This went through a driver that had slew rate control so that the flanks of the signal were sloped to a good 20% or so of the pulse period of the FSK signal. By the time the signal was fed through the transformer onto the wire it had a general appearance of a sine wave. At least it was OK for transmission very long distances over the wire to the opposite end. As a matter of fact the longer the wire the more sine wave looking the received signal looked! I didn't explicitly mention it before but the FSK transmission in this example was half duplex with one frequency pair used for transmit and another frequency pair used for receive. I do not recall exactly the freqencies involved but they were something like 800/1200 Hz for one direction and 1800/2200 Hz the other direction. That design was done on an 8051 type part at 22MHz with a 1x clocking.