It has been my experience that you will burn up FETs if you depend upon the MCU FW to close the loop between the detection of the current level and the removal of the FET drive signals upon overload detection. You are much better off to let specific circuitry do this that is capable of measuring the peak current levels allowed and provide cycle-by-cycle cutout on overload conditions. Speaking from practical experience here.

That now said let's concentrate on the measurement of the current sense output of the driver. An effective way that I have found to do this is to use a sample and hold chip. The input to the S/H is the current sense voltage output pin of the driver. The output in turn drives the A/D input of the MCU. The sample/hold control input is driven from a timed pulse that is derived from the PWM drive signal. It can be a good idea to delay the sample window to start part way into the active time of the PWM pulse after the initial transient has settled down some and the current becomes more stable. Another short delay can be used to generate the sample pulse width window for the S/H chip. At the termination of the sample pulse time it is appropriate to initiate the A/D conversion. It is best to utilize A/D conversion techniques where the start convert is driven from a logic signal derived from the sample window control signal. As long as the A/D converter can complete a conversion before the next PWM pulse starts everything will work out nicely. (If the conversion takes longer then it is necessary to add logic to keep the S/H chip from resampling on every single PWM pulse).

The delay times and sample window generation can be implemented in a number of ways. The simplest is often the best strategy and will be possible if the PWM frequency of the motor drive is kept at a fixed timing frequency. In this case timing can be generated from use of tiny gate logic with R/C delays and Schmidt trigger buffers. You may also need several two input gates to generate a clean sample window gate pulses and start convert pulse. If the PWM timing is variable then you may have to resort to using a couple of interconnected programmable counter/timer channels.

Also do not forget that if the PWM signal can transition to very narrow duty cycles of active time that it could get shorter than the time of the delayed sample and hold gating pulse. In this case you may need to provide a scheme to ignore A/D readings in this timing zone.

Michael Karas