| ??? 06/04/10 16:34 Read: times |
#176389 - so exactly when does the hardware check the interrupt regs Responding to: ???'s previous message |
Erik Malund said:
No I/O function (UART, timer, whatsoever) causes an interrupt!
the UART just set TX, RX, the timers just set TF, ..... This help clarify the process in my mind. Thanks! Erik Malund said:
Then the processor at certain times in the instruction cycle check these flags and the IE and the previous instruction and possibly decides to vector to an ISR.
So, to address your actual question, whatever the EA does, it will never disable the setting of a TF and it will never reset it. Erik So to address the question behind the question, when does the uC hardware check the interrupt flag registers? Once per instruction? Once per machine cycle? The 8051 documentation seems to indicate that there is something magical that happens under two specific circumstances; the instant an interrupt flag is raised and on the RETI instruction. But based on experimentation and the discussion so far, this is clearly a misinterpretation. Is it that the classic 8051 behaved that way and most or all modern implementations are more sophisticated, checking the interrupt registers regularly? --David |
| Topic | Author | Date |
| Interrupt Hardware checked on SETB EA? | 01/01/70 00:00 | |
| Yes... | 01/01/70 00:00 | |
| the way to see it | 01/01/70 00:00 | |
| so exactly when does the hardware check the interrupt regs | 01/01/70 00:00 | |
| VERY derivative dependent | 01/01/70 00:00 | |
| Datasheet should tell you | 01/01/70 00:00 | |
| ports? machine cycle? | 01/01/70 00:00 | |
Still the datasheet will say. | 01/01/70 00:00 |