Every FPGA design I've ever done, and will probably do, has at least one state machine.

I cannot tell you whether these machines are Mealy, Moore or Manchurian. And it really doesn't matter. Teaching Mealy vs Moore state machines forces the engineer to fit some academic paradigm that has no real world benefit.

All of my state machines have synchronized inputs and have registered outputs. State transitions are based on whatever's necessary. Sometimes the machine is in one state and skips right to the next state. Sometimes it'll spin in one state, waiting for a counter to expire. Sometimes it'll spin in one state, waiting for some external process to set a flag. Whatever makes the most sense for the task at hand.

One thing I NEVER do and NEVER recommend is the use of the two-process (or God forbid, three-process!) state machine, the sort with a clocked process for output registering and current-state update, and a second combinatorial process for handling state transitions and new output assignment. Those are simply unmaintainable and a recipe for disaster.



An intern once asked me about Karnaugh maps. I said, with a straight face, "I have a computer that does that for me!"

Doing logic minimization by hand is certainly a worthy skill if you're going to write a synthesis tool.

-a