A good ring buffer implementation, that makes sure that the indices are atomically readable don't need to turn off the interrupts since the insert index has one owner and the remove index has another owner. The ISR can insert a received character while the main loop is busy picking up a previously received character. And the ISR can pick up an outgoing character while the main loop is busy adding one more character to send.

Careful data designs can greatly affect the needs to lock memory accesses. This is extra important for an 8051 chip compared to 16-bit or 32-bit processors that can perform larger memory accesses atomically.