??? 10/01/09 04:47 Read: times |
#169319 - This was the Exact Problem Responding to: ???'s previous message |
Maarten Brock said:
You already found out that the interrupt vector for timer 2 is not at the same place as for an intel 8052. Yet you still include < 8052.h >. Who knows what else they moved around. (Well, since I looked, I know. ET2 is at 0xE8 instead of 0xAD.) I think you'd better include < p89v66x.h >. It contains the correct sfr and sbit definitions. Maarten The program works now! I have hard coded the sfr and sbit definitions and the interrupt is generated. Here is the updated code: #include <8051.h> #define WAIT 1 #define READY 0 #define CLEAR 0 #define SET 1 volatile bit ovf = 0; /* record the overflow */ volatile bit bit_status = READY; void isr_byte_recv(void) __interrupt 7; __sfr __at (0xC9) T2MOD; __sfr __at (0xC8) T2CON; __sfr __at (0xCA) RCAP2L; __sfr __at (0xCB) RCAP2H; /* T2CON register bits */ __sbit __at (0xC8) CP; __sbit __at (0xC9) CT2; __sbit __at (0xCA) TR2; __sbit __at (0xCB) EXEN2; __sbit __at (0xCE) EXF2; __sbit __at (0xCF) TF2; __sbit __at (0xE8) ET2; main() { T2CON |= 0x01; EXEN2 = 1; EA = 1; ET2 = 1; TR2 = 1; while (1) { /* my application code here */ } } void isr_byte_recv(void) __interrupt 7 { if (TF2 == 1) { /* check overflow */ P1_5 = !P1_5; /* LED2 */ TF2 = 0; } if (EXF2 == 1) { P3_4 = !P3_4; /* buzzer */ EXF2 = 0; } } Thank you all for your suggestions. This is a new lesson. cheers, Sarma |
Topic | Author | Date |
Timer 2 Interrupt Enable? | 01/01/70 00:00 | |
do you actually clock the T2EX? | 01/01/70 00:00 | |
Yes I am | 01/01/70 00:00 | |
prototype visible to main | 01/01/70 00:00 | |
Some Differences Found in Documentation | 01/01/70 00:00 | |
who know the most about NXP chips ? | 01/01/70 00:00 | |
Can't Get Your Point | 01/01/70 00:00 | |
YES | 01/01/70 00:00 | |
One Problem Fixed | 01/01/70 00:00 | |
wrong include | 01/01/70 00:00 | |
This was the Exact Problem | 01/01/70 00:00 | |
re include files![]() | 01/01/70 00:00 | |
Please check .RST file | 01/01/70 00:00 |