??? 06/19/09 03:13 Read: times |
#166237 - update Responding to: ???'s previous message |
I spoke to the Honeywell Engineer today. He sent me scope data from all 4 lines and the data I'm seeing at each of the port pins is identical.
After spending much of the day going through every possible scenario and disabling the 'h' command sent to the compass, it seems that I am in fact off by one bit per pulse, not two like I had orignally thought. My processor has live hardware debugging and stepping through the code line by line has brought something to my attention. After configuring the SPI port and enabling SPI, I noticed that the "SPI Busy" flag was being set by hardware before an SPI transfer had started. Because I configure the clock line as idle low per the compass' data sheet, I think it was seeing the fact that the CLK line is actually high before the CS pin is pulled low and assumed the SPI port was busy. Should I include pull down resistors on the clock and data lines to pull them low when a transfer is not taking place? I am wondering if that could be the cause of my missing bit? I have tried turning SPI off then back on right before pulling CS low to clear the Rx buffer bit count but that didn't help. Will reading the data in the buffer before the count reaches 8 bits clear the buffer? I do not have direct access to the buffer but there must be a way to flush it just prior to initiating the data transfer? What else could it be? Your thoughts would be greatly appreciated. Thanks again, Brian |
Topic | Author | Date |
SiLabs C8051F500 and SPI | 01/01/70 00:00 | |
answered in crosspost at silabs forum | 01/01/70 00:00 | |
Please help? | 01/01/70 00:00 | |
it could be | 01/01/70 00:00 | |
Slave | 01/01/70 00:00 | |
Have you tried ... | 01/01/70 00:00 | |
thank you | 01/01/70 00:00 | |
Juat a thought | 01/01/70 00:00 | |
compass | 01/01/70 00:00 | |
update | 01/01/70 00:00 | |
just for fun/verification![]() | 01/01/70 00:00 |