Dear Esteemed 8052 experts,

We've been successful with an Archimedes 4.23g version compiler (IAR origin), last updated in 1993, and have seen no need to upgrade in all this time, and have a variety of products produced in this well-known environment.

The question has arisen: If we were to buy maxim's board that has the DS80C400 mounted on it incl. reference designs, could we not just re-compile our existing code and get the compiler to "see" the flat memory space in 24-bit paged memory mode? This way we could just bridge the board to a backplane with direct access to a large ROM. My understanding of this mode is that it uses an SFR that indicates which 'page' the code is on. I've tried taking one of our projects, and recompiling it into a large memory model (from banked) and the assembly output does not seem to show any hook that replaces the LCALL/LJMP instruction as it does in banked mode - if it did this, I'd be able to handle the jumps myself. So, I ask myself, why not leave it in banked mode, but I'm concerned that leaving it in banked mode would lead to some confusion because the addresses keep being reused.

To take advantage of the chip would require purchasing a new compiler toolkit (probably IAR - opinions anyone?), porting the code (from IAR to present level IAR), a new ICE (Phyton - opinions anyone?) ... big $$$.

Comments, anyone?