Hi,

I am using 128K EPROM in my project with 2 code banks. I am also using 64K RAM.
The parameters generated as per keil listing file :

	BL51 BANKED LINKER/LOCATER V6.15, INVOKED BY:
	C:KEILC51BINBL51.EXE COMMON {.outputSTARTUP.obj}, COMMON {.outputL51_BANK.obj}, COMMON {.outputmic40.obj}, BAN
	>> K0 {.outputLine40.obj}, BANK1 {.outputprint40.obj} TO .output96v1 BANKAREA (0X2E10, 0XFFFF) REGFILE (.output9
	>> 6v1.ORC) PRINT (.Listing96v1.m51) RAMSIZE (256) BANK0 (?CO?LINE40 (0X8000), ?PR?MAIN?LINE40 (0XFF00)) BANK1 (?CO?PR
	>> INT40 (0X8000))  
 
 

The modules are : Common - ?CO?MIC40
Bank0 - ?CO?LINE40
Bank1 - ?CO?PRINT40

	LINK MAP OF MODULE:  .output96v1 (?C_STARTUP)


            TYPE    BASE      LENGTH    RELOCATION   SEGMENT NAME
            -----------------------------------------------------

            * * * * * * *   D A T A   M E M O R Y   * * * * * * *
            REG     0000H     0008H     ABSOLUTE     "REG BANK 0"
            REG     0008H     0008H     ABSOLUTE     "REG BANK 1"
            REG     0010H     0008H     ABSOLUTE     "REG BANK 2"
            REG     0018H     0008H     ABSOLUTE     "REG BANK 3"
            DATA    0020H     0002H     BIT_ADDR     ?BA?MIC40
            DATA    0022H     0008H     BIT_ADDR     ?BA?LINE40
            BIT     002AH.0   0002H.7   UNIT         ?BI?LINE40
            BIT     002CH.7   0002H.4   UNIT         ?BI?MIC40
                    002FH.3   0000H.5                *** GAP ***
            DATA    0030H     0020H     UNIT         _DATA_GROUP_
            DATA    0050H     0019H     UNIT         ?DT?MIC40
            IDATA   0069H     0001H     UNIT         ?STACK

            * * * * * * *  X D A T A   M E M O R Y  * * * * * * *
            XDATA   0000H     F625H     UNIT         ?XD?MIC40
            XDATA   F625H     079BH     UNIT         ?XD?LINE40
            XDATA   FDC0H     00C8H     UNIT         ?XD?PRINT40

            * * * * * * *   C O D E   M E M O R Y   * * * * * * *
 
 

-- and so on.


Q1. What does ' X D A T A M E M O R Y ' specify in the above listing?
Q2. How to manage between xdata variable defining in one module and using as 'extern' in other module.

For example, I defined xdata variables in my project as follows:

In common module(MIC40) header:

		typedef struct trunk_def
		{
			unsigned char enable;
			unsigned char id;
			unsigned char type;
			unsigned char count;
			unsigned char on_enable[2];		
			unsigned char off_enable[2];
			unsigned char cs_denied[12];
			unsigned char cs_allowed[12];
			unsigned char access[96];

		}T_GROUP;

		T_GROUP  xdata t_group[24];

		typedef struct alarm_time
		{
			unsigned char hrs;
			unsigned char mins;
			unsigned char secs;
			unsigned char day;
			unsigned char month;
			unsigned char year;
			unsigned char week;
			unsigned char alarm_applied;

		}ALARM_TIME;

		extern ALARM_TIME xdata alarm[96]; 

 
 

-----------------------
In banked modules:

		typedef struct trunk_def
		{
			unsigned char enable;
			unsigned char id;
			unsigned char type;
			unsigned char count;
			unsigned char on_enable[2];		
			unsigned char off_enable[2];
			unsigned char cs_denied[12];
			unsigned char cs_allowed[12];
			unsigned char access[96];

		}T_GROUP;

		extern T_GROUP  xdata t_group[24];

		typedef struct alarm_time
		{
			unsigned char hrs;
			unsigned char mins;
			unsigned char secs;
			unsigned char day;
			unsigned char month;
			unsigned char year;
			unsigned char week;
			unsigned char alarm_applied;

		}ALARM_TIME;

		ALARM_TIME xdata alarm[96]; 	


 

The structures and variables are created in the modules as per their frequency of usage.
Q.How will the compiler handle these?
Q.Should both definitions be first defined in common module and be defined as 'extern' in Banked modules?

thanks