What are FPGAs and CPLDs and how are they used?
Submitted By: Jez Smith FAQ Last Modified: 10/27/07
- What is programmable logic and how is it used in embedded systems?
As the name suggests programmable logic devices(PLDs) can be thought of as logic devices in which the actual function is not defined at the time of manufacture but is defined by a designer who is using it as part of some larger design. The designer specifies the functions to be carried out by the programmable logic device, converts those specifications into a description of those functions which can be understood by a logic compiler and then the logic compiler converts the description into a programming file which is loaded into, and configures the programmable logic device (PLD) so that it performs the desired function. This is clearly a very simplified description of the process involved.
Choosing the programmable logic device.
The first thing the designer does is to specify exactly what functions are to be carried out by the logic in the PLD, and the types of functions which can be implemented are only limited by the designers imagination and quite possibly his budget. At this stage we can start to get a feel for how complex the design is going to be in terms of how much logic is involved and start to think about the type of device which is going to be needed to implement the desired functions. Clearly a very simple function such as address decoding or a memory mapping function is going to only use a few logic gates, while a large counter or a memory controller is going to require a large number of logic gates ,plus some flip-flops, memory and so on. Luckily PLD manufacturers are aware of this which is why there are various types of PLD available.
What types of PLD are available?
There are three main types of PLD in general use today.
The Programmable Array Logic (PAL) The Generic Array logic (GAL)
The earliest and most basic of programmable logic devices.
The basic structure of the Programmable Array Logic is an array of 2^n-1 n input AND gates driving a n input OR gate. The AND gates produce the logic product of its connected inputs. When unprogrammed all of the AND gates inputs are connected by fusible nickel-alloy links. The overall logic function of the programmed device is determined by a sequence of link rupturing steps which are performed by a device programmer under computer control prior to insertion of the PAL into the circuit.
There are several variations on this basic theme available such as devices with registered outputs, and devices where the AND gates drive NOR gates instead of OR gates. Typically these devices have between 8 and 16 input and output pins and are used for very small logic functions which would perhaps require a handful of medium scale integrated logic devices.
2; The Complex programmable Logic Device (CPLD)
As the name suggests CPLDs are more complex than PALs. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations. In common with the PAL device the CPLD has a non-volatile configuration memory and is ready to function immediately on system start-up. For all but the largest devices, routing constrains most logic blocks to have input and output signals connected to external pins with little opportunity for internal state storage or deeply layered logic. CPLDs have typically the equivalent of tens of thousands of logic gates, and provision for more complex feedback between logic cells and logic for implementing commonly used functions such as counters, adders and multiplexors.While the PAL/GAL type devices usualy but not always have the programmable AND array and fixed OR array type structure CPLDs typicaly have a programmable AND gate array and a programmable OR gate array within each macrocell which means that the product terms can be shared between macrocells thereby increasing the CPLDs overall flexability.
3. The Field Programmable Gate Array (FPGA)
With its roots in the CPLD devices of the early ‘80s the main differences between the FPGA and the CPLD apart from the number of equivalent logic gates available in a FPGA, which can run into the tens of millions, are architectural. FPGA architectures can be said to be dominated by interconnect making them far more flexible in the range of designs which can be implemented in them and far more complex to design for than CPLDs. The other major architectural difference is the presence of embedded high level functions such as multipliers, memories interfaces and even embedded processors.
Until recently FPGAs were always implemented with a volatile configuration memory which meant that the device had to be reconfigured by an external memory each time the system was restarted, recent developments have lead to non-volatile flash based FPGAs which do not suffer from this drawback.Many FPGA vendors now produce devices which can be partialy or completely reconfigured on the fly by an external microprocessor or memory device.One common use of CPLDs is to act as a boot device which is used to configure the main FPGA on system start up.
CPLDs typicaly have highly predictable timing as the interconnections between the macrocells are less configurable than in an FPGA,FPGAs on the other hand have highly variable timing and one of the main tasks of the designer is to ensure that the design meets its timing requirements(timing closure)
Because of the huge number of different PLDs available there is an increasing blurring of the distinctions between the PAL/CPLD/FPGA structures, some large CPLDs have features found in FPGAs and some PAL/GAL type devices have features found in CPLDs
How do I design with PLDs?
PLD Design and Programming.
The designer providing either a schematic design or a functional description written in a hardware description language defines the PLD behavior. The two most common HDL’s are VHDL and Verilog. A netlist is produced using the PLD vendor’s EDA tool set, and the netlist can then be fitted to the actual PLD in a process called place and route. VHDL stands for VHSIC Hardware Description Language, and VHSIC in turn stands for Very High Speed Integrated Circuits. For historical reasons Verilog tends to be more in use in the Far East and the US while VHDL is more in use in Europe. Some people will say that Verilog is easier to use as its not as strongly typed as VHDL and doesn’t allow such extreme levels of abstraction as VHDL.
Asyncronous verses syncronous design.
Most digital designs used today are syncronous, that is they use a central clock signal in order in syncronize the operation of the design and ensure that data is transfered between sections of a design on a timely basis, although it is possible to design digital circuits which do not utilise a clock and they do have many remarkable properties which make them attractive,see here for a detailed discusion of asynronous system design http://hdlplanet.tripod.com/comp_arch..._adv_async
however some programmable logic devices are not suited to this design technique and the lack of suitable design software makes this an area which is sadly neglected, most designers are taught to avoid this area of design altogether, this situation is slightly improving with many university groups carrying out research into the area which may with time lead to asyncronous design tools becoming more widely available.
Typically the designer will simulate the design at multiple stages throughout the design process. Initially the register transfer description in VHDL or Verilog is simulated by creating test benches to stimulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is laid out in the FPGA or CPLD at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist. The most common simulation tool used today is MODELsim from Mentor Graphics. http://www.model.com/
In order to simplify the design process vendors will typically provide libraries of predefined functions, although these functions usually known as IP or intellectual property cores are not cheap but some websites such as http://www.opencores.org do provide access to IP cores released under the GPL or similar licenses.
It is, of course, possible to implement a 8052 microprocessor or any other microprocessor as an IP core within an FPGA which opens up a whole range of possibilities such as an entire system design being contained within a single device. This allows great flexibility and has very desirable properties in terms of reliability and manufacturability.There are several synthesisable 8052 softcores and many other usefull synthesisable and behavioural models(used in simulation) available from the the Hamburg VHDL archive, typicaly availaible under the GPL or similar licences http://tams-www.informatik.uni-hamburg.de/vhdl/ Increasingly manufacturers of PLDs are producing very coarsely grained devices such as the Xilinx Virtex 4 which are aimed squarely at system on a chip type designs and in an attempt to ease the learning curve and increase the abstraction level of the design are producing EDA tool sets which can implement designs directly from standard C or C with extensions for parallel processing. systemC http://www.systemc.org/ is one such example, the main critisims levelled at these tools is that they provide a 'behavioral' description rather than a register transfer description of the design and as such they are difficult to optimise and the behavioral logic compilers are still in their infancy.
There are two methods of implementing an FPGA with an embedded CPU core, the first known as a softcore is a processor written as a parameterisable function such as the MicroBlaze and the Nios from Xilinx and Altera respectively. Other FPGAs contain dedicated CPU hardware ,known as a hardcore CPU, such as selected Xilinx Virtex devices which have upto 4 built in IBM PowerPC405 microprocessors. Clearly the dedicated hardware CPU will always outperform the softcore, also the dedicated hardware CPU does not use any FPGA programmable resources.Zylogic semiconductor corporation http://www.zylogic.com.cn/english/tools03.htm produce a range of FPGA devices with an embedded 8052 hardcore. One interesting device although not directly related to the 8052 is the Atmel FPSLIC which is an AVR processor embedded into an Atmel FPGA, the most noticable difference between the two offerings is that the Atmel device is fine-grained reconfigurable.
Advantages of hard/softcore microprocessors.
The ability to incorporate a microprocessor into the fabric of the FPGA has many advantages:-
Firstly cost reduction, the cost of producing and testing a printed circuit board is closely related to the number of holes, vias and layers that the circuit board requires. Clearly if we can incorporate an entire design into a single device then this greatly reduces these costs.
Secondly design security, if a product is going to be introduced into a very competative market where it is highly likely that a competitor is going to try to reverse engineer the design then implementing the entire design in an FPGA where the inbuilt encryption function is used means that the design is now an impenatratable black box where the internal circuitry and the 8052 firmware is completely hidden from view.Actel http://www.actel.com promotes its non-volatile flash based FPGAs as being highly secure.
thirdly the ease with which a softcore can be modified means that extra features such as non-standard instruction sets can be implemented.
Lastly when a design incorporating an FPGA is produced in very large numbers it becomes feasable to consider converting the FPGA design into an application specific integrated circuit(ASIC) as this is a complex process there are companies which will perform this service at a fairly realistic price such oxford semiconductors http://www.oxsemi.com
It is worth noting that as with anything else in life you get what you pay for when dealing with IP cores, in particular IP cores released under the GPL or similar type of licences there is no gaurantee that the core will work for your chosen device without some modification, quite often these cores are incomplete and are often entirely unsupported, that in itself is perhaps a good reason to pay for a professionaly written and supported core,only the end user can deside if they have the skills to make any modifications that might be required.
While PLD manufacturers do make claims to be able to clock their devices at very high speeds it is worth noting that in practice the speed that your design will run at is very much dependant on the coding style, clumsy code will result in clumsy structures,most PLD vendors often offer advice on good coding practice in the form of application notes.
PLD Manufacturers.
The three major players in the PLD market place are: -
Xilinx http://www.xilinx.com
Altera http://www.altera.com
And lattice http://www.latticesemi.com
Not a major manufacturer but...
http://www.achronix.com/ producers of very high speed,extreme enviroment and radiation hard FPGA devices (up to 2 Ghz)
Further reading
http://www.klabs.org/richconte...torial.pdf : - tutorial on FPGA and CPLD architecture
http://www.opencores.org : - open source IP cores.
http://tams-www.informatik.uni-hamburg.de/vhdl/ :- everything you ever wanted to know about VHDL but were afraid to ask,plus synthesisable and behavioural models.
http://hdlplanet.tripod.com/vhdl/vhdl.html : -VHDL reference.
http://hdlplanet.tripod.com/verilog/verilog.html : - Verilog reference.
http://www.doulos.com/knowhow/v...uide/tips/ :- design tips.
How about an example?
Submitted By: Russ Cooper FAQ Last Modified: 10/27/07
- The thread here describes a complete beginner's experience in building a Morse code decoder using Verilog.
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